Electrochemical deposition may be employed at various points in the integrated circuit (IC) fabrication and packaging processes. At the IC chip level, damascene features are created by electrodepositing/plating copper within vias and trenches to form multiple interconnected metallization layers. Above the multiple metallization layers, the “packaging” of the chip begins. Various wafer level packaging (“WLP”) structures may be employed, some of which contain alloys or other combinations of two or more metals or other components. For example, the packaging may include one or more “bumps” made from solder or related materials. A typical example of a plated bump starts with a conductive substrate seed layer (e.g. a copper seed layer) having an “under bump” diffusion layer of plated nickel (e.g. 1-2 μm thick and about 100 μm wide) under a film of lead tin solder plated pillar (e.g. 50-100 μm thick and about 100 μm wide). After plating, photoresist stripping, and etching of the conductive substrate copper seed layer, the pillar of solder is carefully melted or “reflowed” to create a solder “bump” or ball attached to the under bump metal.
As an alternative to this scheme (often referred to as “copper pillar” or “micro pillar”), an under bump of a non-solder plated “pillar” metal such as copper, nickel, or a combination of these two, is created below a typically much thinner and smaller solder film than above. In this scheme, useful in achieving tight/precise feature pitch and separation control, the copper pillars may be for example 50 μm or less in width, features separated from one another by 75-100 μm center to center, and the copper may be 20-40 μm in height. On top of the copper pillar, a nickel barrier film, e.g., about 1-2 μm thick, is sometime used to separate the copper from the tin containing solder and thereby avoid a solid state reaction to form various mechanically and chemical undesirable bronzes. Finally, a solder layer, typically 20-40 μm in thickness is added. This scheme also enables a reduced amount of solder for the same features size, reducing cost or total amount of lead (in lead containing solders) in the chip.
Lead-tin materials provide good quality “bumps” for packaging and are very easy to plate. Unfortunately, environmental and health-safety concerns regarding lead's toxicity is driving a movement away from the use of lead containing solders. For example, the RoHS initiative (Directive 2002/95/EC of The European Parliament) requires entities to change from the established tin-lead process to a lead free one. Logical replacement bump materials include indium, tin, tin-silver binary materials, tin-bismuth binary materials, and tin-silver-copper ternary materials. Materials based upon tin alone can suffer from a number of fundamental limitations and application difficulties, such as the tendency to form large single grained balls with varying crystal orientations and thermal expansion coefficients, and “tin whiskers” which can lead to interconnect-to-interconnect shorting. The binary and tertiary materials may perform better and alleviate some of these pure tin issues, potentially, at least in part, by precipitating a large number of small grain inclusions of the non-tin component as part of the solder melt to solid state freezing process. Certain compositions made from silver-tin alloys, may demonstrate these characteristics. Thus, silver-tin solder alloy bumps are of particular interest.